Hemin Rahimi

Hemin Rahimi

Hardware Design | Low-Power & Low-Latency | Security & Reliability
Kurdistan, Iran.

About

Highly accomplished Digital Electronics Engineer with an M.Sc. and over 8 years of combined research and teaching experience, specializing in advanced digital system design, verification, and hardware development for FPGAs and ASICs. Expert in RTL design, algorithmic implementation, system optimization, and low-power/low-latency architectures, consistently delivering high-performance solutions. Proven ability to lead multidisciplinary research, translate complex concepts into tangible hardware, and drive innovation in secure and reliable systems.

Education

University of Kurdistan
Sanandaj, Kurdistan, Iran

→

M.Sc.

Electronics Engineering

Grade: 17.29/20

Courses

CMOS

VLSI

DSP

Low Power Design

Data Communication Networks

Image Processing

Technology of Semiconductor Fabrications

University of Kurdistan
Kurdistan, Kurdistan, Iran

→

B.Sc.

Electronics Engineering

Grade: 15.91/20

Courses

Design of ASIC and FPGA Systems

Computer Architecture

Logic Circuit analysis and design

Digital Systems Test and Testability

Engineering Statistics and Probability

Microprocessors

Digital Telecommunication Systems

Analog Electronics

Awards

Top Student (Rank 1)

Awarded By

University of Kurdistan

Awarded for achieving the highest academic standing in the Master of Science in Electronics Engineering program.

Top Student (Rank 3)

Awarded By

University of Kurdistan

Recognized for outstanding academic performance, ranking third in the Bachelor of Science in Electronics Engineering program.

Publications

TSM⁺ and OTSM: Correct Application of Time-Shared Masking in Round-Based Designs

Published by

IACR TCHES

Summary

Co-authored a paper on the correct application of time-shared masking in round-based designs, advancing cryptographic security.

Effective fault detection in 3D ICs: cluster-based BIST for enhanced inter-layer via fault coverage

Published by

FITEE

Summary

Co-authored a paper on cluster-based BIST for enhanced inter-layer via fault coverage, improving fault detection in 3D ICs.

One More Motivation to Use Evaluation Tools, This Time for Hardware Multiplicative Masking of AES

Published by

DATE2025

Summary

Co-authored a paper exploring further motivations for using evaluation tools in hardware multiplicative masking of AES, with accompanying repository and paper.

A Novel Approach for Offline and Online Application-Dependent testing of FPGA interconnects

Published by

iicm2023

Summary

Co-authored a paper introducing a novel approach for application-dependent testing of FPGA interconnects.

An evolutionary approach to implement logic circuits on three dimensional FPGAs

Published by

ESWA

Summary

Authored a paper detailing an evolutionary approach for implementing logic circuits on three-dimensional FPGAs.

SA-based Approach to Implement Digital Systems on 3D Integrated Circuits

Published by

ISEE

Summary

Authored a paper on a SA-based approach for implementing digital systems on 3D Integrated Circuits.

Implementation of digital circuits on three dimensional FPGAs using Simulated Annealing

Published by

ISES2020

Summary

Authored a paper on the implementation of digital circuits on three-dimensional FPGAs using Simulated Annealing.

Work

Technical University of Darmstadt
|

Research Assistant

Darmstadt, Hesse, Germany

→

Summary

Led advanced research in low-latency cryptographic designs and developed robust hardware countermeasures against physical side-channel attacks.

Highlights

Conducted cutting-edge research on low-latency cryptographic designs, enhancing security and performance for critical applications.

Developed and implemented hardware countermeasures, effectively mitigating physical side-channel attacks at ImpSec Group.

Co-authored two peer-reviewed papers (first author), contributing to advancements in secure and reliable digital systems research.

University Of Kurdistan
|

Lecturer & Research Assistant

Kurdistan, Kurdistan, Iran (Islamic Republic of)

→

Summary

Instructed undergraduate electrical engineering courses and spearheaded research initiatives in digital design and 3D FPGAs.

Highlights

Lectured undergraduate courses including Computer Architecture, Logic Circuits, and Digital Systems Design, delivering foundational knowledge to engineering students.

Led impactful research in hardware design, resulting in 5 publications in conferences and journals.

Mentored and guided numerous students in complex digital design projects, fostering hands-on experience and academic growth.

University Of Kurdistan
|

Teaching Assistant

Kurdistan, Kurdistan, Iran (Islamic Republic of)

→

Summary

Supported instruction for over 10 core electrical engineering courses, facilitating student learning and practical skill development.

Highlights

Assisted in teaching over 10 core electrical engineering courses, including ASIC/FPGA Design, C++ Programming, and VLSI.

Provided direct support to students, clarifying complex concepts and guiding practical exercises to enhance comprehension and application.

Contributed to the development of course materials and lab sessions, improving the learning experience for undergraduate students.

Kurdistan Telecommunication Company, Data Center
|

Data Center Intern

Kurdistan, Kurdistan, Iran (Islamic Republic of)

→

Summary

Analyzed and optimized the performance of critical central equipment within a data center environment.

Highlights

Examined the performance of central equipment at high temperatures, identifying key areas for operational improvement and reliability.

Proposed and evaluated solutions to address temperature-related performance issues, enhancing system longevity.

Gained practical experience in data center operations and critical infrastructure management, contributing to system stability.

Projects

From RTL to GDSII: Design a Round-Based PRINCE Cipher

→

Summary

Executed a complete RTL-to-GDSII implementation of a round-based full PRINCE cipher using industry-standard tools.

3D Convolution Hardware Implementation

→

Summary

Designed and verified a parameterizable 3D convolution core with automated functional verification using MATLAB co-simulation.

Implementing RISC-V Processor using Verilog-HDL

→

Summary

Implemented and verified a RV32I core using Verilog-HDL, ensuring functional correctness with industry tools.

FPGA-Based OFDM Link Optimization through Frequency, Clock, and Timing Offset Corrections

→

Summary

Developed and implemented CFO, SCO, and timing offset correction algorithms on a Virtex-7 FPGA for OFDM link optimization.

Interests

ASIC/FPGA Design

Low-power digital design, Hardware-algorithm co-design, Design-for-test, Architectural challenges in 3D ICs.

Cryptography

Post-Quantum Cryptography, Implementation security, Side-channel analysis, Lightweight and efficient cipher architectures.

AI Hardware

RISC-V for SNN acceleration, Memristive and emerging devices, Energy-efficient edge AI systems.

Skills

Operating Systems

Linux, Windows.

Programming Languages

C/C++, Verilog, Python, Bash Scripting.

EDA & Development Tools

Vivado, ModelSim, Cadence Virtuoso, Cadence Genus, Cadence Innovus, Synopsys HSpice, Synopsys Design Compiler, PROLEAD, Yosys, VTR, Git.

Software & Libraries

MATLAB, Atmel Studio, Visual Studio Code, TensorFlow.

Hardware Prototyping

FPGA Programming, AVR Programming, Soldering, Laboratory Equipment.

Languages

Persian

Native

English

Proficient

Kurdish

Native

References

Amir Moradi, Ph.D.

Full Professor, Chair for Implementation Security, Department of Computer Science, Technical University of Darmstadt, 64293 Darmstadt, Germany. Email: amir.moradi@tu-darmstadt.de.

Hadi Jahanirad, Ph.D.

Associate Professor, University of Kurdistan, Department of Electrical Engineering, Sanandaj, Kurdistan, Iran, Postal Code 90210. Email: h.jahanirad@uok.ac.ir.

Mohammad Razaghi, Ph.D.

Full Professor, University of Kurdistan, Department of Electrical Engineering, Sanandaj, Kurdistan, Iran, Postal Code 90210. Email: m.razaghi@uok.ac.ir.